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Process and Layout Dependent Substrate Resistance Modeling for Deep Sub-Micron ESD Protection Devices Xin
Zhiping Yu, and Robert W. Dutton Department of Electrical Engineering, Stanford University, Stanford, CA 94305 *Silicon Technology Development, Texas Instruments Inc. Dallas, TX 75265 Tel: (650)723- 1482 Email: [email protected]
This paper demonstrates a new methodology for bringing accurate substrate resistance modeling into circuit level ESD simulation. The impact of layout and process variations on the effective substrate resistance of deep sub-micron ESD devices is analyzed and modeled using a quasi mixed-mode approach. The substrate resistance simulated by this method shows good agreement with the values extracted from experimental data. This technique can be employed to simulate turn-on characteristics of ESD protection devices and determine the impact of process and layout variations on their reliability before fabrication of the actual devices.
I. INTRODUCTION During electro-static discharge (ESD), the magnitude of substrate resistance determines the on/off state of the parasitic bipolar transistor (n+-p-n+ or p+-n-p+), which provides protection by forming a current path from the drain to the source and substrate. More importantly, the interactions of different circuit elements through the common substrate can have a significant impact on the circuit's ESD performance. Therefore, accurate modeling of the substrate resistance to capture the effects of layout and process is essential for performing accurate circuit level ESD simulation. Moreover, the fact that the substrate resistance becomes conductivity modulated due to the injection of minority carriers into the base after the turn-on of the parasitic BJT also needs to be modeled in order to simulate the substrate current correctly [l-21. The effects of conductivity modulation can be seen from experimental data, which shows that the substrate current continues to increase after snapback; hence, to maintain a constant base voltage of the parasitic BJT, the substrate resistance must decrease [I]. Instead of explicitly modeling the dynamic substrate resistance, the standard approach is to model the substrate potential as a current controlled voltage source [2-41,
Substrate Contact Fig. 1 Compact model for simulating MOSFET breakdown uses a current controlled voltage source to represent the dynamic substrate resistance during ESD stress.
and Ids is the MOSFET's surface current under normal operating condition. Rsub and Rd are circuit model parameters that can be extracted from experimental data as illustrated in Fig. 2 . Rsub is the substrate resistance at the on-set of the snapback, and it is extracted using the y-intercept, "beon Rsub=Is ubo
Is u bo
where Vbeon is the turn-on voltage (-0.8V) of the base and emitter junction of the parasitic BJT and IsubO is the y-intercept. Rd models the conductivity modulation by relating the substrate current (Is&) to the total drain current (Id), and it is extracted using the slope,
as shown in Fig. I, where the reduction of the substrate resistance due to conductivity modulation has been implicitly modeled. is the substrate current, Id is the total drain current, 0-7803-5860-0/00/$10.0002000IEEE
IEEE 00CH37059 38"Annual lntemational Reliability Physics Symposium, San Jose, California,2000 I
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2. The straight line fitting slope . I , + y - intercept ) is a good approximation to extract Rsub and R, parameters from Is& vs. 1, plot, which is obtained at V,=OV. ( Isub =
where Nlsub - is the slope. The R, . (I, - I,,) term is negligible N,
until after the snapback, after which, it begins to offset the R s u b . Isub term to keep the substrate potential constant, emulating minority carrier injection into the substrate. This substrate potential model can estimate the reduction of the substrate resistance due to conductivity modulation; however, once extracted, the Rsub and Rd are fixed parameters that fail to predict the effects of layout and process variations, and they must be extracted again from experimental data for a different layout or process. Other approaches employ substrate resistance networks to simulate the effects of different layouts [5-61. Without accounting for conductivity modulation, they overestimate the substrate resistance and underestimate the substrate current, which could lead to inaccurate simulation results for the second breakdown as shown in Fig. 3. Hence, it is desirable to formulate a methodology that can account for conductivity modulation, process, and layout variations in substrate resistance modeling to allow for improved circuit simulation capabilities. The aim of this work is to extend the capability of the current controlled substrate potential model (Vsub model) using the quasi-mixed-mode (qmm) method so that the Rsub and Rd parameters can be simulated for different layouts and processes based on a few calibrated devices, instead of extracting them from experimental data. This allows the accurate modeling of the substrate resistance due to the effects of layout and processes, and enables the circuit designers to simulate and design an effective protection device based on layout and identify critical current path during the ESD stress. In this paper, the qmm method is calibrated against a single, fixed-geometry device with one doping profile. The calibrated doping profile
Fig. 3 The ESD I-V curve (solid line) is obtained using a constant substrate resistance ( Vsuh = Rsub . I s u b ) without considering conductivity modulation. The discrepancy between the simulated results and the experimental data (circles) is significant.
Substrate Contact Fig. 4 This is the schematic representation of hole injection (Igen) into the structure for the device simulation part of the qmm. It is equivalent to sweep Igen while fixing vd.
is used as a basis to simulate Rsub and Rd parameters of other
Substrate Contact I
Initialize Construct 2D cross-section of ESD device Set-up Boundary Conditions Ground gate, source, and substrate contact Apply voltage at drain terminal
f ’ 3’I ‘ I
hole inJiCtio? by photogeneration
1 Simplified Device Simulation Calculate injection area (for each drain bias) Inject Igenas holes into p-substrate
Fig. 5 With the boundary conditions established, the full device simulation can be greatly simplified by using photogeneration function to replace hole generation by impact ionization. This corresponds to steps 2 and 3 of Fig. 6.
Compute Rsub and R, Extract from Is& vs. Id curves from device simulation Circuit Level Simulation Import Rsub and Rd as function of vd Implement lumped element model
devices with different layouts (i.e. channel length and source to substrate contact spacing variations) and p-well doping. The simulated Rsub and R, are compared to the extracted Rsub and Rd, showing the accuracy of the qmm method. The qmm methodology is briefly described in section two; in section three, the qmm approach is applied to model the substrate resistance of on-chip ESD devices with layout and process variations. The extracted substrate resistance parameters are discussed along with their significance in section four, and followed by the conclusions in section five.
11. QUASI-MIXED-MODE APPROACH The quasi-mixed-mode model is a marriage between device and circuit simulation. It differs from the traditional mixed-mode (devicekircuit) simulation by not using a fully coupled matrix approach. The qmm utilizes the circuit model and device simulation to model lumped and distributed elements respectively . For a given technology, the process dependent parameters do not vary once extracted, so the physical effects can be modeled as lumped elements; hence, the impact ionization model (M) parameters are implemented directly in the compact model along with the parameters that govern normal MOSFET operation. On the other hand, the substrate resistance parameters tend to depend on layout; therefore, it is better suited to use distributed element modeling. The device simulator computes the substrate resistance based on layout. The compact model takes the simulated substrate resistance, and simulates the resulting ESD I-V curve. The qmm was developed with the purpose of modeling substrate resistance of the protection device, and it is much faster, robust and easier to calibrate compared to the full de$ice simulation. In addition, the substrate resistance are able to account for layout and process -s% parameggs
Done Figure 6. The flow diagram illustrates the system level set-up of the quasi-mixed-mode model.
variations which extends the capabilities of the circuit model described in the introduction. Hence, the qmm can be used as an effective tool in designing the optimal ESD devices without building and testing them on silicon. The speed improvement, robustness, and ease of calibration are possible because the device simulation part of the qmm does not simulate with impact ionization model. The qmm breaks the feedback loop caused by impact ionization: instead of stressing the drain terminal as in normal simulation (Fig. 1) or measurement set-up, the drain voltage is fixed while sweeping the Igen until the parasitic BJT is on as shown in Fig 4. This is equivalent to the snapback region, where the drain voltage is roughly constant, while the currents change quite dramatically. This process of sweeping I, can be accomplished by proper placement of the boundary conditions in device simulation . Fig. 5 illustrates the placement of boundary conditions on the ESD devices. The gate, source, and substrate contacts are all tied to the ground, and the drain terminal is biased to establish the corresponding electric field and depletion area. The holes are injected into the depletion region that has the highest electric field around drain junction, much like the mechanism of hole generation by impact ionization. The hole injection is achieved using photogeneration function. For the Igen sweep, it can be shown that during snapback when the 297
p-substrate Fig. 7 ESD devices have two different types of layouts: changing Lch (channel length) with fixed L,, (source to substrate contact space), and changing L,, with fixed Lcb Table 1. Devices A-L have the same layout dimensions, aside from the different dimensions listed. All the dimensions listed in the Table 1 are in pm. Process X differs from process Y only in p-well dose. Devices A-F are fabricated using process X, and devices G-L are fabricated using process Y,
for circuit level simulation. The compact model shown in Fig. 1 is implemented inside the circuit simulator. The circuit parameters for normal MOSFET operation and impact ionization are already extracted from experimental data according to previously published research [2-4,8].
Fig. 8 The LDD and S/Djunction depth and lateral diffusion ratio along with p-substrate doping are scaled in the direc-
111. CALIBRATION AND SIMULATION OF SUBSTRATE RESISTANCE
parasitic BJT is on at every Vd with V,=O,
I g e n = I b + I sub
Id = I C + ' g e n
where I,, Isen, Id, Ib, and Isub are as shown in Fig. 4 and 5. The information flow of the quasi-mixed-mode model is described in Figure 6. To begin with, a 2D cross section of the ESD device is constructed using the device simulator. Then boundary conditions are imposed on the device that allow the holes to be injected into the silicon substrate as described earlier. The placement of boundary conditions and the execution of device simulations are automated by using computer scripts. After running device simulations, a set of substrate current (Isub) vs. drain current (Id) curves under different drain bias are obtained. The values of substrate resistance parameters (Rsub and Rd) can be extracted from these curves as a function of drain bias (Vd) according to eq. (1) and (2), and imported into the compact model as , 298
In this work, the qmm is applied to model the substrate resistances of ESD devices fabricated by state-of-the-art CMOS technology with two different p-well dopings. Process X has a lower p-well doping than process Y. These ESD devices are all 20ym wide with varying gate lengths (LcJ or source to substrate contact spacings (Lpn), as illustrated in Fig. 7. The exact layout dimensions along with the process information of each device are listed in Table 1. An analytical doping profile for process X is tuned until the simulated Rsub and Rd parameters fit the experimental parameters of device A. No additional change is made to the doping profile and model coefficients after this calibration. The calibrated doping profile was used to predict the substrate resistance of devices (B-F) fabricated under the same process X. To simulate the effect of p-well doping variation on Rsub and Rd parameters, the doping profile for process Y was generated by simply scaling the doping profile for process X according to the ratio of the two p-well doses,
Fig. 9 Experimental Is& vs. Id curves obtained with gate grounded for devices A&B showing the impact of increasing the distance of substrate contact to source contact (Lpn)on the magnitude of Rsuband Rd parameters.
Fig. 11 Experimental Is& vs. Id curves for devices c (plotted in circles, Lch=0.18pm)) and D (plotted in squares, Lch=0.21km) show the impact of increasing channel length
(Lch)on the magnitude of Rsub and Rd parameters.
exp. data for process X 0 exp. data for process Y
eqs. (2) and (3) as shown in Fig. 9, and the Rsub and Rd parameters of devices G&H were extracted using the same method [2-4,7]. The predicted Rsub values obtained using qmm method are plotted against the extracted Rsub as shown in Fig. 10. The experimental Rsub and Rd parameters for devices C&D were extracted as shown in Fig. 1 1 , and similarly the Rsub and Rd parameters of devices E&F and I-L were extracted using the same method. The predicted Rsub and Rd values obtained using qmm method are plotted against the extracted Rsub and Rd as shown in Figs. 12 and 13 for process X and Y respectively.
6 Lpn (Pm)
Fig. 10 The resistance values plotted in circles and squares are extracted from experimental data of devices A&B and G&H fabricated using process X and Y, and the resistance values plotted in triangle and diamond shapes with dotted lines are extracted from the simulation results of A&B and G&H. The error between the simulated and experimental data is -15%.
as shown in Fig. 8. The device simulation part of qmm was performed using MEDICI, and the circuit simulation part was done using HSPICE. After performing the qmm simulation as described in the previous section, the Rsub and Rd parameters were extracted from the simulation results. The experimental Rsub and Rd parameters for devices A&B were extracted based on
IV. EFFECTS OF LAYOUT AND PROCESS VARIATIONS From the extracted experimental values in Fig. 10, it can be observed that as the distance from the source to substrate contact (Lpn) increases, the substrate resistance (Rsub) becomes larger. This is due to an increase in the effective substrate area. However, the slope ( Al,Tub/Ald) remains the same as shown in Fig. 9 because the property of the parasitic BJT has not been altered by changing the Lpn. In addition to Rsub increase due to Lpn,the simulation results also captured the fact that Rsub decreases as the p-well doping increases for process Y. The error is -15% for Rsub values of devices B and H of which 3% is propagated by the calibration error from device A. The current flow contours are plotted for both devices A and B in Fig. 14. It indicates that as the substrate contact
exp. data for process X
.&- - sim. data for process X
exp. data for process Y
-A- sim. data for process Y A.
8 5 80%?15
Fig. 12 The resistance values plotted in circles are extracted from experimental data of devices C-F fabricated using process X, and the resistance values plotted in triangles are extracted from the quasi-mixed-mode simulation results. The maximum error between the measured and experimental data does not exceed 6%.
Fig. 13 The resistance values plotted in circles are extracted from experimental data of devices I-L fabricated using process Y, and the resistance values plotted in triangles are extracted from the quasi-mixed-mode simulation results. The maximum
moves further away from the NMOS (from 2.5pm to lOpm), the current flow path also becomes more spread out, and more current flows deeper through the bulk of the substrate (P+ substrate), such as devices B and H. And this could also explain the larger percentage of the simulation error for devices B and H (15%) compared to devices A and G (5%) because the initial calibration done for device A did not accurately calibrate the doping of P+ substrate, since Isub of device A did not flow as deep through the substrate. It is well known that the current flows along the least resistive path, and in this case, the current path is mainly determined by the location of the substrate contact; hence, the spreading resistance determines the Rsub values. The qmm approach was able to take this nonlinear effect due to layout into account when modeling the substrate. In this case, two experimental data points of Rsub (Fig. IO) per process is not enough to find the influence of L,, on Rsub for design analysis; therefore, additional structures are simulated using the qmm method. The simulated Rsub
parameters are plotted against corresponding Lpns as shown in Fig. 15. From the plot, it is clear that as the substrate contact is moved further from the NMOS (larger L,, values), Rsub values do not increase as rapidly since most of the substrate current is flowing through P+ part of the substrate. The precise analytical and physical relationship between L,, and Rsub still needs to be formulated with the aid of more simulations and experiments. According to Figs. 12 and 13, the experimental data and the simulation results for both processes demonstrate that Rsub decreases and R , increases as channel length (Lch) increases, which shows that the simulation results are in good agreement with experimental data. As the p-well doping increases for process Y, the magnitude of simulated Rsub values in Fig. 13 also decreased compared to that of Fig. 12 (process X). The percentage errors for devices C-F and I-L, which all have different Lch, are less than 9%. The error could be caused by the inaccuracies in the 2-D doping profile.
error between the measured and experimental data does not exceed 9%.
and the injected hole current (Ige,) flows from the drain junction towards the substrate contact. And the substrate spreading resistance (&b) can be estimated by , 1 Rs,b’p
= 2(W - Lch)ln Lch(W + 2T) Oc
x . + Xd/2 IW(i)
where p is the substrate resistivity, T i s the substrate depth, Xi is the junction depth, x d is the depletion width at the drain junction, w is the channel width, and LCh is the channel
Lateral Distance (km) Fig. 14 The current flowlines are plotted for devices A&B. The distance from NMOS to substrate contact is 2.5pm for device A and lOpm for device B. Most of the current still flows near the surface for both devices, the remaining current spreads out much deeper (3.6 pm vs. 1.7 pm) for device B than A.
length. The exact relation between L ’ and Lch in eq. (9) depends on the hole current distribution inside the substrate, and it can be obtained by empirically fitting calculated Rsubs (eq. (8)) to the experimental values . Eqs. (8) and (9) demonstrate that the magnitude of Rsub decreases with channel length. On the other hand, Rd (slope) increases because the p of the parasitic BJT decreases more rapidly as the drain current increases for shorter channel length as shown in Fig. 16. It also can be shown that during snapback [3,8,10],
I 3.5 n
As p decreases due to high current injection for both the short and long channel devices such as devices C and F, M increases for both as governed by eq. (10) to keep the increases, but IgenC < I g e n F parasitic BJT on; therefore, Igen
Fig. 15 Rsub values between I-lOpm Lpns are obtained using the qmm method. As L,, increases beyond 4pm, there is a decrease in the slope of the curve, showing a reduction in incremental Rsub value.
As illustrated in Fig. 2 and eq. (2), R,,b is the substrate resistance at the turn-on of the parasitic BJT (i.e. I, = I, = 0). At that point, eq. (4) reduces to,
because pc> pF at each Id according to Fig. 16 . Ib also increases as p decreases, but the rate of increase for IbF is c the rate of decrease of PF is less than that of I ~ because much less than that of pc; hence, the slope of the ISub vs. Id curve decreases as the sharp drop in p requires more Zb (eq. (12)) from I,,, for shorter channel device. The beta degradation in both devices C and F is caused by high current injection after the parasitic BJT turns on. During this process, the injection of electrons into base is sufficient to cause a significant increase in the hole concentration in the base, thereby reducing the collector current (Ic). The base charge under high current injection can be described by [lo],
where P N , ( x ) d x is the gummel number (the initial built in base charge caused by the processing of the transistor), XB is the width of the quasi-neutral region of the base, and
Lch=0.18p.m (Device C)
n ( x ) is the injected electron concentration. Based on eqs. (13) and (14), device F with larger Lch, has a larger gummel number than device C, resulting in a lower p as shown in Fig. 16, but for incremental p change (p degradation) during high current injection, the device with a larger gummel number is less affected by the injected electrons than the device with a smaller gummel number; hence, the p degrades at a slower rate for longer channel device. The magnitude of R,,b and Rd are very sensitive to the process and layout changes as can be seen from Figs 10, 12, and 13, and that reflects in the shapes of ESD I-V curves. For example, in order to quantitatively predict the effects of increasing Lch from 0.18p.m (device C) to 0.30p.m (device F) on the ESD I-V curve without fabricating device F, R,,b and Rd from device C had to be used. Using the qmm method, Rsub and Rd for device F can be predicted resulting in a more accurate ESD I-V curve as shown in Fig. 17.
Lch=0.30p.m (Device F) I 4
Fig. 16 p for devices C and F are extracted from the qmm simulation results. p of device C decreases at a much faster rate than device F; hence, the percent increase in 1, is larger as the Id increases for device C.
V. CONCLUSIONS In conclusion, we have demonstrated a quasi-mixedmode approach to accurately model the substrate resistance parameters, Rsub and Rd, across different layouts and processes for deep sub-micron ESD devices. This methodology can be used to evaluate different layout and technology options for optimizing the performance of ESD protection devices before fabrication. It can be extended to model the common silicon substrate of the protection circuit to capture the substrate coupling effects between different circuit elements and also define the turn-on process for multifinger devices.
cxp. &t;i I;Kdwiw 1'
- qmm sim. results for device F
- -. siin. results using dcvicc C's HSuh and Kd
ACKNOWLEDGEMENT The authors would like to thank Sridhar Ramaswamy and Charvaka Duvvury from TI for giving valuable suggestions and comments. Finally the authors gratefully acknowledge the support from SRC and TI.
REFERENCES Fig. 17 The ESD I-V curve of device F (solid line) is simulated using the values of Rsub and Rd obtained from the qmm method, and the simulation results matches the experimental data of device F (circles). The dashed line shows discrepancy between the simulated curve and the experimental data using the Rsub and Rd of device C. The discrepancy will get larger as the layout becomes more different.
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